1. Field of the Invention
This invention relates to clock generators and more particularly to adjusting the frequency of signals generated by the clock generator.
2. Description of the Related Art
A wide variety of electronic products have clock generators or synthesizers to generate the clock signals utilized by the electronic products. A typical clock generator utilizes a phase-locked loop (PLL) supplied with a reference signal from a source such as a crystal oscillator. The output frequency of the signal supplied by the clock generator or synthesizer can be determined by a divider value of the feedback divider in the PLL. Thus, a reference frequency supplied to the PLL is “multiplied” based on the divider value to generate the synthesized clock frequency.
Several types of divider circuits have been utilized in PLLs. One kind of divider is the integer-N divider in which the input signal is divided by an integer number. For example, FIG. 1A illustrates the timing diagram of several integer divides including a divide-by-two, a divide-by-three and a divide-by-four. The signal being divided is CLKin. Note that no jitter is introduced in the frequency division process, other than noise from circuit non-idealities. FIG. 1B illustrates the simple integer divide-by-two provided by a D flip-flop (DFF) 151.
Another type of PLL architecture uses a fractional-N divider. FIG. 1C illustrates a timing diagram of fractional-N frequency division. Fractional-N frequency division allows use of a non-integer divisor by changing the integer divide value according to the fractional portion of the divisor. That is, a stream of integer divides are performed that approximate the desired ratio. For example, FIG. 1C illustrates a timing diagram of a divide-by-2.25. The input clock (CLKin) is shown as waveform 101 having a period of one unit interval (UI). The output of the fractional-N divider is shown in waveform 103. As shown in waveform 103, the divide-by-2.25 is achieved by a sequence of divide-by-two for three periods and a divide-by-three for one period, assuming a first order delta sigma modulator is used to control the fractional-N divider. Waveform 105 illustrates the ideal waveform for a divide-by-2.25. The quantization noise of the modulator, at the output of the fractional-N divider is shown as the difference at 107, 109, and 111, between the actual output of the fractional-N divider shown in waveform 103 and the ideal output for a divide-by-2.25 shown in waveform 105.
One technique for supplying control signals to a fractional-N divider is to use a delta-sigma modulator to supply a divide sequence to the fractional-N feedback divider. The fractional-N divider receives a divide value sequence corresponding to a desired divider value. The fractional-N divider supplies the divided signal to a phase detector with noise associated with the nature of the fractional-N divider. In fractional-N clock synthesis, the fractional-N noise may be filtered out by the PLL loop. In addition, phase error correction may be utilized to address the jitter introduced by the divider by introducing an offset into the PLL corresponding to the jitter generated by the fractional-N divider.
However, the clock synthesizers described above may have limited frequency coverage (integer dividers) and/or require a complex loop filter and complex VCO control that increase the cost in design effort and chip area, resulting in more expensive products that may be too expensive in cost or real estate for significant portions of the clock synthesizer market and/or lack flexibility in operation.